The present invention is directed to an input buffer circuit and, more particularly, to a rail to rail differential buffer input stage that has operational characteristics that are maintained for common mode input voltages varying over substantially the whole voltage difference between the voltages at the power supply rails.
A rail to rail differential buffer input stage may be used to drive an operational amplifier or a comparator for example. Such circuits are increasingly required to operate with reduced power supply voltages, especially in very large-scale integrated (VLSI) circuits. At the same time, larger variations of common mode analog input voltages are encountered, due to noise levels from neighboring digital circuits. The differential buffer input stage provides differential output currents that can be summed to amplify the differential input signal, and block the common mode voltage variations from the output signal.
One configuration of a rail to rail differential buffer input stage includes n-type and p-type input differential pairs of transistors, such as metal-oxide semiconductor field effect transistors (MOSFETs), which are connected in a voltage follower configuration to the power supply rails. The n-type input differential pair conduct when the common mode input voltage is closer to the high power supply voltage and the p-type input differential pair conduct when the common mode input voltage is closer to the low power supply voltage. When the common mode input voltage is at a value intermediate to the high and low power supply voltages, both the n-type and p-type input differential pairs conduct and the transconductance of the input stage, that is to say the variation in its differential output current for a small unit variation in differential input voltage, is double the transconductance gm of a single input differential pair. However, n-type and p-type dummy pairs of transistors, which are driven by the common mode input voltage but not by the differential input of the input stage, can be added in parallel with the n-type and p-type input differential pairs of transistors. One or the other of the dummy pairs conducts when the common mode input voltage is not close to the intermediate voltage and diverts the tail current directly to the output of the stage and away from the respective input differential pair, switching it OFF, so that the transconductance of the input stage corresponds to the transconductance gm of the other, single input differential pair. When the common mode input voltage is close to the intermediate voltage, both the dummy pairs of transistors conduct, halving the tail current and the transconductance gm of each of the respective input differential pairs, and the total transconductance of the input stage is maintained at an almost constant value of gm.
The intermediate voltage at which the dummy differential pairs are turned ON and OFF can be a fixed voltage, defined by a resistor chain forming a voltage divider connected between the power supply rails. However, the resistance of the voltage divider must be high to avoid high static current consumption, which consumes a large area of the semiconductor chip. This and other ways of generating the intermediate voltage also cannot adapt readily to the effects of manufacturing process variations on the characteristics of MOSFETs, especially if these are run at sub-threshold voltages.